Integrated circuit memory devices are widely used in consumer and commercial applications. As is well-known to those have skill in the art, many integrated circuit memory devices include active devices such as transistors, and capacitors for storing data. As is also well-known, the integration density of integrated circuit memory devices has increased, so that more and more integrated circuit memory cells may be formed in an integrated circuit chip.
In general, as the number of devices formed on a chip increases, the size of the devices tends to shrink. For example, 1 GB DRAM cells which include a transistor and a capacitor, may have an area on an integrated circuit of about 0.3 .mu.m.sup.2. This is about the area of a single contact hole in a 1 MB DRAM cell. Accordingly, it is desirable to reduce the area of the transistors, the capacitors and the contact holes in order to produce high capacity memory cells, such as a 1 GB DRAM cell.
State-of-the-art memory cells may employ three-dimensional cell structures, so that the contact holes, the capacitor and the transistor can be included in a small area. Since these three-dimensional cells may be scaled down in the lateral dimension, more cells can be crammed in an integrated circuit. Unfortunately, however, since the scale-down in the vertical direction is typically not large, the aspect ratio of the contact holes which are used to interconnect memory devices in the integrated circuit may increase. The resistance of the contacts may thereby increase, which may limit the device performance.
Other developments in high density memory devices attempt to increase the capacitance per unit area by providing a high dielectric material or by providing a three-dimensional capacitor structure. For example, it is known to use a Capacitor Over Bitline (COB) structure, wherein it is possible to obtain high capacitance in a limited area by forming a bitline and then forming the cell capacitor on the bitline.
FIG. 1 is a cross-sectional view of a portion of a conventional DRAM device employing a COB structure. The DRAM device includes a cell array region at the right side of FIG. 1 and a peripheral circuit region at the left side of FIG. 1.
As shown in FIG. 1, a capacitor is formed by forming a storage contact hole through a first interlayer dielectric 20 on an integrated circuit substrate 10 on which a word line 12 is formed. A storage electrode 24 is then formed to electrically contact the storage contact. A dielectric film 26 is formed on the storage electrode 24 and a plate electrode 28 is formed on the dielectric film 26. In the capacitor, the storage contact and the storage electrode 24 may be formed at the same time. The storage contact may include a plug which is formed of a doped polysilicon layer, which is the same as the material for forming the storage electrode.
Continuing with the description of FIG. 1, after providing a second interlayer dielectric film 30 on the capacitor and forming a contact hole through the second interlayer dielectric film and the first interlayer dielectric film 20, a first wiring layer 32 is formed. The first wiring layer 32 may be formed of a refractory metal such as tungsten, and is generally used as a first level interconnect wiring layer. A second wiring layer 34 and a third wiring layer 36 may then be formed by conventional processes, using appropriate interlayer dielectric films.
Unfortunately, as shown in FIG. 1, a memory device employing a COB structure may produce a step height between the cell array region (at the right side of FIG. 1) and the peripheral circuit region (at the left side of FIG. 1). This step height may become larger when the height of the storage electrode 24 is increased in order to increase the capacitance of the capacitor. As such, it may be difficult to reliably fabricate the first, second and third metal wiring layers 32, 34 and 36 respectively, to overcome the step height difference.
Capacitor On Metal (COM) memory devices have also been proposed, among other reasons, to overcome the potential step height problems. In a COM structure, the capacitor is formed on a first level metal wiring layer. A COM memory device is described in a publication entitled "A New Capacitor on Metal (COM) Cell for Beyond 256 Mega Bit DRAM" by Yoon et al., 1994 Symposium on VLSI Technology Digest of Technical Papers, pp. 135-136. In the Yoon et al. publication, it is possible to reduce the vertical pitch of the metal wiring layer and yet still secure the desired cell capacitance. However, as the integration density of integrated circuit memory devices continues to increase, additional improvements are desirable.